Many of today's static n-channel MOS memory integrated circuits use only one power supply from which the substrate potential is created via an on-chip substrate voltage generator circuit. The substrate potential is the most negative potential used with the memory and results in a back gate bias on the MOS transistors which stabilizes threshold voltages and thus limits leakage caused by subthreshold conduction. Limiting subthreshold conduction is particularly important for memory cells in which the power dissipation is in the subnanowatt range. A failure of the power supply causes the substrate potential to also fail. Typically, an auxiliary power supply, such as a battery, is automatically substituted for the main power supply if there is a failure therein. This auxiliary power supply maintains the stored information in the memory and retains the substrate potential (provided the substrate voltage generator circuit is also connected to the battery) such that transistor back gate bias is maintained. In order to reduce power drain on the battery, all of the circuits (including the substrate voltage generator) of the memory other than the memory cells are disconnected from the battery. This results in increased subthreshold conduction through the MOS memory because of the loss of transistor back gate bias and can result in the loss of stored logic information.
In very low power dissipation static MOS memories a loss of transistor back gate bias can cause an increase in leakage currents due to increased subthreshold conduction which is comparable in magnitude to the quiescent current levels of the memory cells. As a result stored logic information is lost. The connecting of the battery to the substrate voltage generator circuit when the main power fails would improve the subthreshold conduction problem; however, power drain on the battery would be significantly increased.